About the program

The VLSI Design with Verilog and VHDL is a comprehensive Internship program that covers fundamental concepts in VLSI design using two prominent Hardware Description Languages Verilog and VHDL. Seven hands on experiments covering topics such as logic gate implementation, flip-flop design, FSM implementation, FPGA implementation, VHDL subprogram exercise, a comprehensive VHDL project, and a simulation and verification exercise. This internship is tailored to provide hands-on experience in designing and implementing complex digital circuits using Verilog and VHDL, ensuring a well-rounded skill set in the VLSI domain.

Perks

Provision of a Learning Android app by Technotran. Provision of a login for the Learning Management System portal. Provision of an internship completion certificate

Who can apply?

Only those candidates can apply who:

1. are from Any,
2. and specialisation from Any,
3. are available for duration of 2 Months
4. have relevant skills and interests

Terms of Engagement

There is a nominal fee of Rs. 800 It is mandatory to maintain a 75 percentage of attendance requirement.

Number of openings

100