About the program

The VLSI Design with Verilog and VHDL is a comprehensive Internship program that covers fundamental concepts in VLSI design using two prominent Hardware Description Languages Verilog and VHDL. Seven hands on experiments covering topics such as logic gate implementation, flip-flop design, FSM implementation, FPGA implementation, VHDL subprogram exercise, a comprehensive VHDL project, and a simulation and verification exercise. This internship is tailored to provide hands-on experience in designing and implementing complex digital circuits using Verilog and VHDL, ensuring a well-rounded skill set in the VLSI domain.

Perks

No Perks, It is an unpaid Internship, We charge Nominal Price For Training and Internship

Who can apply?

Only those candidates can apply who:

1. are from Any
2. and specialisation from Any
3. are available for duration of 2 Months
4. have relevant skills and interests

Terms of Engagement

75% attendance is Mandatory

Number of openings

100