Internship Description
VLSI DESIGN & VERIFICATION INTERN
QURIOUZ MANKEY PRIVATE LIMITED
- Full Time
- 04-Nov-2025
- Hyderabad,
-
Start date
Immediately -
Duration
6 Months -
Stipend
₹0 /month -
No of Credits
0 -
Apply by
15-Nov-2025
About the program
The VLSI Design Verification Internship at Quriouz Mankey Pvt Ltd is an industryoriented program aimed at students who have successfully completed their training in VLSI Design and Verification and wish to gain practical, projectbased experience. Interns will actively contribute to realtime RTL Design and Verification projects within the company, focusing on: RTL Design using VerilogSystemVerilog Functional Verification and Testbench Development Understanding Verification Methodologies UVMOVM Simulation, debugging, and waveform analysis using EDA tools Collaborative design and verification workflows for ASICFPGA systems This internship bridges the gap between academic training and professional application by enabling participants to work on industrygrade design and verification environments. By the end of the internship, participants will gain strong handson expertise in digital design, verification environments, and testbench creation, preparing them for careers in ASIC, FPGA, and SoC development.
Perks
Internship Certificate from Quriouz Mankey Pvt Ltd Real-time project experience in RTL Design and Verification Testbenches Mentorship and guidance from industry experts Opportunity to work on industry-standard EDA tools and methodologies Letter of Recommendation for top-performing interns Eligibility for pre-placement offer based on performance
Who can apply?
Only those candidates can apply who:
- are from B.Tech. / B.E./ Equivalent
- and specialisation from Electrical and Electronics Engineering,Electrical and instrumentation Engineering,Electronics and Communication Engineering
- are available for duration of 6 Months
- have relevant skills and interests
Terms of Engagement
The internship is offered by Quriouz Mankey Pvt Ltd exclusively to students who have successfully completed their training in VLSI Design and Verification. The bond period is 4 months, during which the intern must commit to working with the company without discontinuation. The internship will be conducted in offline mode only at the company premises. Remote or online work is not permitted. Interns will work on real-time RTL Design and Verification Testbench projects, under the guidance of technical mentors and team leads. Interns must maintain punctuality, discipline, and confidentiality throughout the internship duration. All design files, codes, and project deliverables developed during the internship shall remain the intellectual property of Quriouz Mankey Pvt Ltd. Interns will undergo regular technical reviews and performance evaluations to assess progress. On successful completion of the internship, participants will receive an Internship Certificate and may become eligible for a pre-placement offer based on performance. Any form of misconduct, data sharing, or violation of company policy will result in immediate termination of the internship and cancellation of certification.
Number of openings
6